![]() Added new API called addDirectory() to bring multiple HDL files.Added support to bring arrays of Integers or Float values using generic parameter.Added support for Input Port Data types of UFIXED, SFIXED with some manual intervention requires in case of having binary point position greater than 0.Extended support for Input Port Data types of SIGNED, UNSIGNED, BOOLEAN, FLOAT32 and FLOAT64.Major improvements to the Blackbox RTL import flow in to Vitis Model Composer.Enhanced Window Processing Block to target URAM resource.Enhancement to HLS Kernel block to support extended templatized parameters.Margin can be specified through kernel code.Specifying size through GUI or kernel code supported.sync, async, cyclic buffer_1d are supported.Added buffer_1d support as Early Access.Upshift center tap parameter added for FIR Halfband interpolator window and stream blocks.Interpolate Polyphase (TP_PARA_INTERP_POLY) parameter added to Halfband Interpolate block.Decimate Polyphase (TP_PARA_DECI_POLY) parameter added to Halfband Decimator block.Super sample rate (SSR> 1) supported on all stream-based FIR blocks.Added new Window and Stream-based Window Function blocks.Added new Stream-based Dynamic Point FFT block.The tool automatically detects RTP ports and the user no longer needs to specify the RTP ports manually.Use of *.cpp to import a graph is now deprecated.Ease of use enhancements to the AI Engine Graph Import block:.After running the cycle approximate AI Engine simulation, the tool shows the throughput for part of the output data bounded by the cursers in the Simulink Data Inspector.You can now add graph constraints to AI Engine DSP blocks – better implementation control for performance/utilization. ![]() In 2022.2, Vitis Model Composer includes many new feature additions and enhancements. ![]()
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